Creating a High Density VoIP Processor
Short summary:
Creating a High Density VoIP Processor. by Irvind S. Ghai & Murali Venkat advantageous to create shared program memory at Level 2, although each core has a ...
Long summary:
Creating a High Density VoIP Processor by Irvind S. Ghai & Murali Venkat Texas Instruments Incorporated One of the key requirements in any high density VoIP platform is to maximize the totalnumber of channels within a very tight power budget and area form-factor.
The DSPengines used to support PCM or LBR software vocoders are the basic building blocks atthe core of a carrier-class, 1000+ channel box and they are the most replicated componentin the chassis. With each device running hundreds of vocoder-channels simultaneouslysignificant memory for both data and program is required with 24 50 Mbit per device.
Memory has become the largest factor that determines die size and with a count of 50 -100 of such devices on a high-density platform any enhancements to the memorypartitioning and architecture provide a significant return in terms of the overall solution.
To achieve peak performance from such a system, it is recommended that the VoIPprocessor be built around a DSP module typically consisting of a CPU core, elements of amemory system and interfaces to a DMA system. The memory system is usually memoryand cache controllers. With the cores typically offering designers a choice of memoryconfigurations, memory architecture has important consequences on a VoIP system.
Onechallenge designers will face is that the operating speeds of DSP cores have historicallyadvanced at a much quicker pace then the speed of their companion memories. Fig. 1: Harvard Architecture For Single And Two-Level Memory Systems Complicating the equation is the fact that most silicon fabricators offer multiple types ofmemory bit cells in the same silicon process node, each with its own power, speed, anddensity trade-offs. There are dense memory bitcells, which target lower leakage power, but in trade they operate at slower relative speeds.
The faster memory bitcells operate at,or higher, than CPU clock rates. In addition memory designers have attempted to matchmemory speeds to the CPU speeds by designing optimized memory architectures. Fig. 1illustrates single and two level memory systems implementations for Harvard architecturewhere a CPU has separate, independently-accessible memory for instructions and data.
A key technical trade-off for new processor definition is about selecting either the one ortwo level memory systems for a given vertical application, with the best match of area,power and performance. There are three potential combinations needed to implement thememory architecture for the required channel densities: Single-level memory based oneither a fast-memory bitcell or alternatively, a slower more dense-memory bitcell; or optto select a two-level memory to achieve fast memory at Level 1, and dense memory atLevel 2, supporting the same amount of overall memory. Not surprisingly there are unique system implications for these different approaches.
Thefirst deals with the power consumed (see Fig.2) with the three different approachesdiscussed: The two flavors of a ...
Source: www.analogzone.com
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